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Home › SupportCase Studies › Design Guide for using Everspin 1 Gb STT-MRAM with Xilinx DDR4 FPGA Controller

Design Guide for using Everspin 1 Gb STT-MRAM with Xilinx DDR4 FPGA Controller

2020-03-10 13:42:20

Everspin Technologies, the world's leading developer and manufacturer of Magnetoresistive RAM (MRAM), today announced a comprehensive design guide to streamline the integration of its 1 Gigabit (Gb) Spin-transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) product in the storage market place. Xilinx,Inc., the leader in adaptive and intelligent computing, has been supporting Everspin’s STT-MRAM for two generations and enables the 1 Gb STT-MRAM solution using its DDR4 controller in the Xilinx Vivado development environment. 

The Everspin and Xilinx integrated solution provides many benefits, with the design guide and tools structured to address:
• Timing: Reducing operating frequency, increasing row access timing, increasing counter widths and reducing CAS       page sizes
• Power-Up: Enabling anti-scribble mode during calibration
• Power-Down: Scramming or moving all relevant data into the persistent memory array
• Performance: Increasing pipeline depth and data transfer efficiency
• Scripts: Providing Verilog models and other detailed information to get storage OEM’s design up and running              effectively

“MRAM and persistent memory is an increasingly important technology across a broad range of solutions,” said Jamon Bowen, Planning and Storage Segment Director, Data Center Group, Xilinx. “We see many applications where advanced capabilities like power loss protection is critical. It’s exciting to see partners like Everspin make it easy for customers to develop world-class memory sub-systems leveraging the Xilinx platform.”

Everspin’s STT-MRAM devices allow enterprise infrastructure and data center providers to increase the reliability and performance of systems where high-performance data persistence is critical. This is achieved by delivering protection against power loss without the use of supercapacitors or batteries. In addition, the larger density 1 Gb part offers more effective management of I/O  streams, creating a greater level of latency determinism and allowing storage OEMs to significantly improve quality of service of their products. Similar benefits can also be achieved using the 1 Gb STT-MRAM device as a persistent data write buffer in storage and fabric accelerators, computational storage, and other applications.

“We value our partnership with Xilinx and continue to collaborate with them to bring our STTMRAM solutions to market,” said Troy Winslow, Vice President of Sales and Marketing for Everspin. “Providing this design guide and tools will help streamline integration and time to market for our customers in providing enhanced applications for data centers.”

Keywords:  everspin

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